CXMT LPDDR6 has entered mass production, debuting in the Xiaomi 18 Fold, the new flagship phone of Xiaomi. This marks the world's first commercial deployment of LDDR6 in flagship smartphones. The product offers a capacity of 16 GB and supports a maximum data rate of 12800 Mbps, with a rate of 10667 Mbps when operating with the SoC. It delivers sufficient data bandwidth to meet the high-performance computing needs of flagship smartphones and edge devices.

CXMT's mass-produced LPDDR6 packaged chip has a total capacity of 16GB. Based on 16Gb single dies, it is compliant with the JEDEC LPDDR6 standard and packaged in a 1295-ball FBGA form factor. It reaches a maximum data rate of 12800Mbps, delivering 60% * higher bandwidth than the 10667Mbps LPDDR5X, while cutting power consumption by 20%* compared to its predecessor to extend battery life for mobile devices.

*Performance data is from internal testing. The bandwidth uplift is based on peak bandwidth comparison.

The development and mass production of CXMT's LPDDR6 encompass multiple key innovations: 

Design: CXMT's LPDDR6 adopts a dual-channel architecture with 24-bit native I/O in normal mode. Its high-speed interface supports independent per-pin calibration of pre-emphasis and DFE (Decision Feedback Equalization) parameters, working with an intelligent training mechanism to ensure signal accuracy and operational stability under high-speed data transmission.

For power consumption reduction, LPDDR6 features a dual-rail DVFS design that delivers hardware-level voltage separation capability. It also introduces a dynamic efficiency mode to enable intelligent strategy scheduling. These capabilities allow LPDDR6 to maintain an optimal power efficiency ratio across varying workloads, providing flexible memory support for mobile devices that require both high computing power and long battery life.

In terms of RAS, in addition to the original Link ECC and On Die ECC features, LPDDR6 adds new functions including Per Row Activation Counting (PRAC)  to defend against row hamnmer attacks, and Memory Built-In Self-Test (MBIST), leveraging multiple mechanisms to ensure data integrity and system stability.

DTCO:  Through DTCO (Design-Process Co-Optimization), over 100 deep optimizations were applied to key circuits and layout design rules (LDR) in the CMOS region, enabling smaller, higher-performing CMOS transistors that support higher bandwidth and lower power requirements.

Packaging: A 1295-ball FBGA PoP package is utilized for LPDDR6's back-end manufacturing. With a solder ball area 50% larger than LPDDR5's 496-ball FBGA counterpart, the package inherently brings higher manufacturing complexity. For the molding process, High-K EMC is employed to encapsulate the entire chip, reducing die thermal resistance by roughly 40%. This greatly boosts heat dissipation efficiency during LPDDR6's high-load operation, fully ensuring stable performance of the memory die. 

Demand for high-speed, low-power memory continues to grow. As the latest generation of low power product, LPDDR6 will support a broad range of future applications, spanning smartphones, PCs, smart wearables, smart vehicles, edge servers and robotics.

The successful rollout of LPDDR6 marks a key milestone in CXMT's high-end memory R&D journey. The product is now scaling for increasing commercial adoption. CXMT will continue to expand its LPDDR6 portfolio with performance, design and process upgrades, and work with industry partners to drive broader LPDDR6 deployment across more scenarios.