CXMT officially announced the mass production of 5th-generation DRAM technology platform (the "G5 Platform") at the 2026 World Manufacturing Convention in Hefei, alongside the debut of new LPDDR5X product lineup based on the platform.

With process capabilities rivaling the industry’s best mass-produced nodes, the G5 Platform is a milestone for CXMT — bringing more innovative memory solutions and greater supply chain resilience to the global semiconductor ecosystem.

Breakthroughs in Process Technology

The G5 Platform has achieved multiple cutting-edge technical milestones across key process metrics.•Half AA pitch: Leveraging an innovative quadruple patterning（SAQP） technology, G5 Platform features an active area half-pitch of 11.95nm for memory arrays, closing the gap with the world’s most advanced volume-production memory platforms.

•Aspect Ratio: Through process flow re-enginering and novel material integration, G5 Platform’s array capacitor aspect ratio reaches 45:1. •Core Area Height: By implementing a DRAM-optimized high-k metal gate（HKMG) process, the G5 Platform successfully shrinks the core cell array height to 6,762 nm.

Built upon existing module process, CXMT developed a digital twin platform spanning design, tape-out, manufacturing, and yield maintenance. In this virtual R&D line, sophisticated DRAM process models are built to accelerate R&D. CXMT G5 Platform also demonstrated advances in several processes including interface engineering, saddle-fin structures, and low-k spacer bitlines.

Next-Generation Product Lineup

The process scaling has driven a significant improvement in the G5 Platform’s die density. G5's DPW(die per wafer) is at least 50%* higher than its previous platform, delivering notable advantages in both power efficiency and cost competitiveness.

Two LPDDR5X products based on the G5 Platform were unveiled at the convention. Both feature a 24Gb per-die capacity, a 50% increase over the previous generation of equivalent products. Offered in 496-ball and 245-ball packaging respectively, the products serve smartphones and portable consumer electronics, and are currently in mass production.

Moving forward, CXMT will remain dedicated to advancing its technology roadmap to meet global demand, delivering next-generation memory products with high performance and robust reliability to support the global digital economy.

Note:

Active area half pitch, capacitor aspect ratio, and core area height reflect actual physical measurement data subject to standard metrology margins of error.

Percentage increases are calculated in comparison with CXMT 4th-generation technology platform. Gross die per wafer (DPW) statistics are normalized to an 8Gb density baseline.